The employment of powerful interfaces, such as an universal serial bus (USB) 3.0, a high-definition multimedia interface (HDMI), or a Thunderbolt, leads to increasing requirements of the electrostatic discharge protection diode (ESD protection diode). In order to maintain an optimum protection in case of an electrostatic discharge, the intrinsic resistance of the protection diode needs to be minimized. Within the concept of a transient-voltage-suppression (TVS) diode, the silicon (Si) below the diode generates a significant portion of the internal resistance of the diode. Thus, a thinner silicon increases the performance of the diode. Currently, conventional manufacturing concepts of such products provide a chip processed on both sides having a chip thickness to be achieved in a front-end-of-line (FEOL) process at wafer level. Subsequently, after the transfer of this wafer to the back-end-of-line (BEOL) processing, each single chip is picked up and soldered onto the leadframe by means of a serial process. Such a serial process is slow and therefore, expensive. A lot of efforts were made to realize a processability within the front-end-of-line processing of thinner and thinner wafers. However, the thicknesses for this kind of diodes which were ideal (e.g. about 20 μm) are not yet controllable by means of conventional manufacturing methods within a volume production. The main difficulties of conventional methods regarding ultrathin silicon wafers are: silicon split-offs during the wafer/chip dicing (e.g. sawing); and fissures in the silicon single crystal caused by means of applying a force (e.g. pressure) such as by means of a pick-and-place process (e.g. during the die attaching).